1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming transistor devices with different threshold voltage levels and various integrated circuit products containing such transistors.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
For many early device technology generations, the gate structures of most transistor elements (planar and FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer (k-value of approximately 10 or greater) and one or more metal layers that function as the gate electrode have been implemented. Such alternative gate structures—typically known as high-k/metal gate structures (HK/MG structures)—have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. Generally, the replacement gate process involves: forming a basic transistor structure (planar, FinFET, nanowire, etc.) with a sacrificial gate structure positioned between sidewall spacers; forming the source/drain regions for the device; performing the necessary anneal process to activate implanted dopant materials; removing the sacrificial gate structure so as to define a gate cavity for the replacement gate structure between the spacers; depositing a high-k gate insulation layer and a plurality of metal layers in the gate cavity; performing a CMP process to remove excess materials positioned outside of the gate cavity; recessing the gate materials within the gate cavity to make room for a gate cap layer; and forming a gate cap layer in the gate cavity above the recessed gate materials. However, as the gate length of transistor devices has decreased, the physical size of the gate cavity has also decreased. Thus, it is becoming physically difficult to fit all of the layers of material needed for an HK/MG replacement gate structure within such reduced-size gate cavities, particularly for NMOS devices, due to the greater number of layers of material that are typically used to form the HK/MG structures for the NMOS devices as compared to PMOS devices. For example, as gate lengths continue to decrease, voids or seams may be formed as the various layers of material are deposited into the gate cavity. That is, as the layers of material for the replacement gate are formed in the gate cavity, the remaining space within the gate cavity becomes very small. As the later metal layers are formed, the remaining space within the gate cavity may be only about 1-2 nm in width or even smaller. In some cases, there may be essentially no remaining space in the gate cavity. This may lead to so-called “pinch-off” of metal layers such that voids or seams may be formed in the overall replacement gate structure, which may result in devices that perform at levels less than anticipated or, in some cases, the formation of devices that are simply not acceptable and have to be discarded.
In manufacturing modern integrated circuit products, transistor devices are sometimes intentionally formed so as to exhibit different threshold voltage levels. In general, a transistor having a relatively lower threshold voltage will operate at a higher switching speed than that of a corresponding transistor with a relatively higher threshold voltage level. Such “low-Vt” (LVT) transistor devices are typically employed in portions of an integrated circuit product where device performance or speed is desirable or critical, e.g., in the logic circuits of an integrated circuit product. Unfortunately, such low-Vt devices tend to exhibit more off-state leakage currents, which means that they consume more power than would otherwise be desired. Thus, all other things being equal, such low-Vt devices are poor choices in applications where reduced power consumption is important, e.g., mobile computing applications, cell phone applications, etc. The opposite is true for so-called “high-Vt” (HVT) transistor devices—they tend to operate at slower switching speeds (a negative) but the off-state leakage currents of such high-Vt devices is less than that of the low-Vt devices (a positive). Such high-Vt devices are typically employed in portions of an integrated circuit product where device performance or speed is less critical, e.g., SRAM circuits. Device designers can also make so-called “regular-Vt” (RVT) transistor devices that have a threshold voltage level that is intermediate to that of the low-Vt devices and the high-Vt devices. Of course, the absolute value of these threshold voltage levels (low, regular and high) may vary depending upon a variety of factors.
Device designers have employed several techniques to intentionally change the threshold voltage levels of transistor devices. One technique simply involves changing the gate length—the distance between the source region and the drain region—of the transistor. All other things being equal, a transistor with a shorter gate length will operate at faster speeds, but it will exhibit higher off-state leakage currents than a corresponding transistor having a larger channel length. Device dimensions have decreased to the point where gate lengths are so small that manufacturing devices with ever smaller gate lengths is very challenging, time-consuming and expensive. Thus, adjusting threshold voltage levels by continuing to reduce the channel length of the transistor devices is becoming more problematic.
Another technique that device designers have used to vary the threshold voltage of transistors involved varying the amount of dopant material used in forming the wells in which the transistors were formed. All other things being equal, the greater the dopant concentration in a well region, the greater will be the threshold voltage of the resulting transistor, and vice-versa. However, in some applications, such as forming FinFET devices, it is very challenging to get the appropriate doping levels, due to random dopant fluctuations and the normal Gaussian distribution of ion implantation processes in general.
Yet another technique that device designers have used to form transistor devices with differing threshold voltage levels simply involves making gate stacks of different materials having different work function values so as to ultimately achieve the desired variation in the threshold voltage levels of the devices. The term “work function” (WF) is commonly used in the art of semiconductor design and manufacturing to refer to the minimum energy needed to remove an electron from the surface of a metal. The work function of a metal is typically a constant characteristic of that metal material and it is usually measured in electron-volts (eV). In general, in CMOS integration schemes using a silicon substrate, a work function metal having a work function near the conduction band edge of silicon (about 4.0 eV) is necessary for NMOS type devices, while a different work function metal having a work function near the valance band edge of silicon (about 5.1-5.2 eV) is necessary for PMOS devices. Thus, in CMOS integration schemes employing high-k gate dielectric materials, at least two types of gate stacks are needed, i.e., a stack of suitable materials that satisfies the individual work function requirements for the PMOS devices and a different stack of materials that satisfies the individual work function requirements for the NMOS devices. As noted above, the gate stack for the PMOS devices provides a flat band voltage closer to the valence band edge of the material of the channel of the PMOS devices, and the gate stack for the NMOS devices provides a flat band voltage closer to the conduction band edge of the material of the channel of the NMOS devices. As is readily apparent, the above-mentioned layer stacking process can become quite unwieldy and complex as more and more versions of transistor devices with different threshold voltage levels are fabricated. Among other problems, etching of metals tends to be more difficult and the different physical heights of the gate stacks of the various devices can cause problems during subsequent processing operations.
Yet another technique involves forming a high-k gate insulation layer (e.g., hafnium oxide) in the replacement gate cavities for each of the various devices; forming a patterned protective metal layer on the high-k gate insulation layer that covers the high-k gate insulation layer in some of the devices while leaving the high-k gate insulation layer exposed in other devices; forming a threshold voltage (Vt) shifting oxide material (e.g., lanthanum oxide) on the exposed portions of the high k insulation layer and on the patterned protective metal layer; forming a metal capping layer above the Vt-shifting oxide material; forming a blanket layer of amorphous silicon above the metal capping layer; and performing a heat treatment to drive material from the Vt-shifting oxide material, such as lanthanum, into the contacted high-k gate insulation layer that is contacted by the Vt-shifting oxide material. In the case where the high-k gate insulation material is hafnium oxide, this process converts the hafnium oxide to hafnium-lanthanum-oxide. The Vt-shifting oxide material, the metal capping layer and the patterned protective metal layer are then removed, and the replacement gate structure is completed by forming additional materials in the gate cavity as previously described. In general, the introduction of lanthanum decreases the threshold voltage level of NMOS devices but increases the threshold voltage level of PMOS devices. In this manner, the threshold voltage levels of the various NMOS and PMOS devices may be adjusted on an integrated circuit product.
Unfortunately, as mentioned above, as the width of the gate cavity has become much smaller, forming the additional materials in the gate cavities to modify the threshold voltages of the devices using a Vt-shifting oxide material, as described above, is becoming even more difficult. The present disclosure is directed to novel methods of forming transistor devices with different threshold voltage levels and various integrated circuit products containing such transistors that may solve or reduce one or more of the problems identified above.